1. Field of the Invention
The present invention relates to memory systems for computers, and more particularly, to methods and apparatus for increasing the execution speed of computer programs.
2. Art Background
In many data processing systems, it is common to utilize a high speed buffer memory, referred to as a "cache" coupled to a central processing unit (CPU) to improve the average memory access time for the processor. The use of a cache is based upon the premise that over time, a data processing system will access certain localized areas of memory with high frequency. The cache typically contains a subset of the complete data set disposed in the main memory, and can be accessed very quickly by the CPU without the necessity of reading the data locations in the main memory.
In data processing systems which employ virtual addressing techniques, a memory management unit (MMU) is coupled between main memory and a cache controller. In the event the CPU attempts to access data which is not disposed in the cache, the cache controller applies a virtual address provided by the CPU to the MMU. The MMU translates the virtual address into a real address, and accesses a particular data location in main memory in which the data is stored. This data is then transferred into the cache and/or provided directly to the CPU. In the case of data comprising computer program instructions, blocks of instructions are typically transferred from main memory into the cache for direct access by the CPU. During the execution of these instructions, it is quite common for branch instructions to be encountered which requires additional branch data to be accessed by the CPU. If the branch data is not currently stored in the cache memory, the cache controller must initiate a memory access to main memory to fetch the branch data so that it may be executed by the CPU. The requirement that branch data be obtained from main memory and stored in the cache and/or provided directly to the CPU reduces the efficiency and speed of the data processing system.
As will be described, the present invention discloses apparatus and methods for reducing instances in which the CPU must halt program execution prior to fetching branch instruction data from main memory. In the present invention, the cache controller scans a block of instruction code for branch instruction, and loads branch instruction data into the cache prior to execution by the CPU.